1. Field of the Invention
The invention relates generally to fault-tolerant digital data processing memory systems and relates more particularly to arrangements for providing automatic sparing of memory modules in said systems.
2. Description of the Prior Art
The provision of fault tolerance in computer memory systems via provision of redundant elements has evolved from cumbersome manual replacement approaches to more automatic substitution techniques. This evolution also has progressed from a provision of at least one redundant component for every on-line replaceable element to a so-called N + 1 redundancy, wherein only one spare is provided for a set (N) of elements, said spare being substitutable for any element of the set.
To be truly automatic, the ideal memory substitution, or so-called sparing arrangement, should be accomplished such that, after the substitution, no changes are required in running the normally operational software programs in the digital data processing system incorporating the memory. Such a characteristic is known as software transparency.
One representative prior art approach to providing spare memory substitution is set forth in U.S. Pat. No. 3,803,560 -- De Voy et al., issued Jan. 3, 1973. In the De Voy method, after error detection and location of a defective module, a spare module is activated and the entire memory subsystem is reconfigured into a contiguous address space. The reconfiguration results in software transparency, but the reconfiguration approach requires rather complex circuitry provided with every system memory module, since the memory configuration utilizes a ripple-through module enabling technique wherein circuitry local to each module modifies an enable address for transmission to succeeding modules.
Another representative sparing arrangement is taught in U.S. Pat. No. 3,633,175 -- Harper, issued Jan. 4, 1972. Harper teaches a defect-tolerant memory system with means for substituting spare memory areas for defective words. The approach is extendable to substitution of multi-word modules, but has the disadvantage of requiring a double-memory-read per fetch operation, since a content-addressable memory is consulted for every memory address to determine if that address points to a defective area of memory. Additionally, with the Harper approach, the spare memory takes up a portion of the available system address range.
Still another prior art approach is represented by U.S. Pat. No. 3,517,171 -- Avizienis, issued June 23, 1970, which teaches so-called power-switching of spare memory modules. Upon location of a faulty module, power is removed from the faulty unit and a spare is automatically cut in, in place of the faulty unit. This power switching approach is more complicated than a logic switching approach and has the added economic disadvantages of requiring complex transfer gating circuitry and one spare memory module for each main memory module.
Hence, there is seen a need to provide a fault-tolerant, digital data processing system memory in a relatively simple and inexpensive manner which will provide for automatic sparing of at least one spare memory module wherein the automatic sparing can be accomplished with software transparency and without decreasing the system's usable address range.